A. Field of the Invention
The present invention relates to a semiconductor device, such as a p-intrinsic-n (PiN) diode or an insulated gate bipolar transistor (IGBT) including a buffer layer formed by proton implantation, and a method for manufacturing the same.
B. Description of the Related Art
Examples of a power semiconductor device include a diode or an IGBT with a breakdown voltage of 400 V, 600 V, 1200 V, 1700 V, 3300 V, or more. The diode or the IGBT is used in a power conversion device such as a converter or an inverter. The power semiconductor device requires low loss, low noise, a high breakdown voltage, and low cost.
FIG. 8 is a cross-sectional view illustrating a main portion of a PiN diode 500 including a general n-type buffer layer 55. As illustrated in FIG. 8, the PiN diode 500 includes an n-type drift layer 52 which is a portion of an n-type silicon substrate 51. A p-type layer, which will be a p-type anode layer 53, is provided in a first main surface of the n-type silicon substrate 51 and an n-type cathode layer 54 and an n-type layer, which will be the n-type buffer layer 55, are formed in a second main surface opposite to the first main surface. Then, a p-type layer 62 (p-type guard ring layer), which will be a high-breakdown-voltage junction termination structure 61, is formed on the first main surface of the n-type silicon substrate 51 so as to surround the p-type anode layer 53. In FIG. 8, reference numeral 58 is an anode electrode, reference numeral 59 is a cathode electrode, reference numeral 63 is a termination electrode, and reference numeral 64 is an insulating film.
The n-type cathode layer 54 needs to have carrier concentration and a diffusion depth required to prevent reach-through of a depletion layer (which means that the depletion layer reaches the cathode electrode 59). For example, the n-type buffer layer 55 which has a higher impurity concentration than the n-type drift layer 52 is formed in the n-type drift layer 52 in order to suppress the spreading of the depletion layer. As a method for forming the n-type buffer layer 55 at a position that is deeper than the n-type cathode layer 54 from the second main surface of the n-type silicon substrate 51 so as to come into contact with the n-type cathode layer 54, a method has been proposed which uses a selenium (Se) atom with a large diffusion coefficient as a dopant ion that is implanted in order to form the n-type buffer layer 55. In addition, as another method for forming the n-type buffer layer 55, a method has been known which forms a hydrogen-related donor using the implantation of hydrogen (H) ions (protons) which have a long range at a relatively low acceleration voltage.
Next, the hydrogen-related donor will be described. When protons are implanted into the n-type silicon substrate 51 (for example, a bulk substrate (wafer) formed by a floating zone (FZ) method) including an oxygen (O) atom, a hydrogen (H) atom and the oxygen (O) atom are combined with a vacancy (V) defect which occurs due to the implantation to generate a composite defect. As a result, a vacancy-oxide-hydrogen (VOH) defect occurs. The VOH defect becomes a donor (hydrogen-related donor) which supplies an electron. When a heat treatment is performed after the proton implantation, the density of the VOH defects increases and donor concentration also increases. Therefore, the n-type buffer layer 55 which has a higher impurity concentration than the n-type drift layer 52 is formed.
An activation process for increasing the donor concentration of the VOH defect can be implemented by low-temperature annealing (heat treatment) which is performed at a temperature of about 380° C. Therefore, a front surface structure which is formed by a high-temperature process is formed on a thick wafer before a thickness reducing process (thinning process) in advance. Then, the rear surface of the wafer is ground and the wafer is thinned to a product thickness. Low-temperature annealing is performed to form a rear surface structure. Since annealing for forming the rear surface structure is performed at a low temperature, it is possible to form a front surface electrode or a passivation film forming the front surface structure on the thick wafer before the thinning process in advance in a process of forming a thin diode or a thin IGBT with a small product thickness. Therefore, in a process after the thickness of the wafer is reduced, only the rear surface electrode forming the rear surface structure is formed. As a result, it is possible to significantly reduce the number of processes after the wafer is thinned.
In the PiN diode 500, the n-type buffer layer 55 is formed in the n-type silicon substrate 51 between the p-type anode layer 53 and the n-type cathode layer 54 so as to be close to the p anode layer 53, and a layer with low carrier concentration remains on the cathode side. This structure makes it possible to improve the storage effect of holes which are minority carriers. As a result, it is possible to form a diode with good soft recovery characteristics even when the n-type drift layer 52 (a region of the n-type silicon substrate 51 between the p-type anode layer 53 and the n-type buffer layer 55) has a small thickness.
The n-type buffer layer 55 can be a thick n-type buffer layer with an equivalently broad carrier concentration distribution in the depth direction by implanting protons into the n-type silicon substrate 51 in different ranges Rp over a plurality of times. PCT Japanese Patent Domestic Re-publication No. 2000-16408 discloses the carrier concentration (impurity concentration) of an n-type layer formed by proton implantation. However, it does not disclose a method for reducing crystal defects caused by proton implantation.
JP 2000-77350 A discloses a method for performing annealing (heat treatment) at a temperature of 350° C. as the method for reducing the crystal defects caused by proton implantation. In US 2006/205,122 A, FIG. 2 illustrates an n-type buffer layer formed by proton implantation in an IGBT. In addition, US 2006/205,122 A discloses that the carrier concentration of the n-type buffer layer formed by changing protons into donors in a proton passage region is not less than the carrier concentration of a substrate.
In the following US 2006/286,753 A, FIGS. 3, 4, and 5 illustrate a thyristor, an IGBT, and a diode which include an n-type buffer layer similarly formed by changing protons into donors. In addition, US 2006/286,753 A discloses a technique which performs a heat treatment at a temperature of 200° C. to 550° C. to recover the crystal defects caused by proton implantation and to change protons into donors.
In US 2006/81,923 A, FIG. 2 illustrates the carrier concentration distributions of a plurality of n-type buffer layers which are obtained by changing protons into donors and are formed in a diode illustrated in FIG. 4 of US 2006/81,923 A or an IGBT illustrated in FIG. 5. In addition, US 2006/81,923 A discloses that the carrier concentration of the n-type buffer layer formed by changing protons into donors in a proton passage region is not less than the carrier concentration of a substrate.
JP 2003-152198 A discloses a technique which forms an n-type buffer layer in a central portion of an n-type drift layer so that a diode has soft recovery characteristics.
However, when the number of stored carriers is small, such as when a small amount of current flows or when the temperature is low, electron concentration is close to donor concentration. Therefore, as described above, even when the n-type buffer layer 55 is formed so as to have a broad carrier concentration distribution, a charge neutral condition (electron concentration=donor concentration+hole concentration) is maintained by the negative charge of the electron and the positive charge of the donor. As a result, the concentration of holes, which are minority carriers, is significantly reduced and the holes are quickly depleted during reverse recovery, which results in a high surge voltage or oscillation.
When the breakdown voltage of the semiconductor device increases, the depth of the n-type buffer layer 55 needs to be more than 15 μm that is illustrated in FIG. 2 of the above-mentioned US 2006/81,923 A, in order to effectively suppress a high surge voltage or oscillation.
However, the acceleration energy of proton implantation needs to be increased in order to increase the depth of the n-type buffer layer 55. When the acceleration energy increases, a defect occurs in a crystal due to implantation damage. When the crystal defect is not recovered by a heat treatment for changing protons into donors, the remaining crystal defect acts as a lifetime killer for the stored carrier and the concentration of the minority carriers (holes) is reduced. As a result, during a switching operation, such as during the reverse recovery of the PiN diode 500 or when the IGBT is turned off, the holes, which are the minority carriers, are quickly depleted and a high surge voltage is generated or the voltage and current oscillate. The oscillation is radiated as radiation noise to the outside and causes an electro-magnetic compatibility (EMC) problem. The crystal defect causes an increase in the leakage current of the PiN diode 500 or the IGBT.
The present invention provides a semiconductor device with a high breakdown voltage which includes an n-type buffer layer with a depth of 15 μm or more formed by proton implantation, has a small leakage current or small generation loss, and can suppress the oscillation of voltage and current during a switching operation and a method for manufacturing the same.